wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 2gb C 2x128mx72 ddr2 sdram unbuffered, ecc w/pll description the wv3hg2128m72eeu is a 2x128mx72 double data rate ddr2 sdram high density module. this memory module consists of eighteen 128mx8 bit stacked bga with 8 banks ddr2 synchronous drams in fbga packages, mounted on a 200-pin so-dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features 200-pin, dual in-line memory module (so-dimm) support ecc error detection and correction fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4200 and pc2-3200 v cc = v ccq = 1.8v 0.1v 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option differential clock inputs (ck, ck#) multiple internal device banks for concurrent operation programmable cas# latency (cl): 3, 4, 5 and 6 adjustable data-output drive strength on-die termination (odt) posted cas# latency: 0, 1, 2, 3 and 4 serial presence detect (spd) with eeprom 64ms: 8,192 cycle refresh gold edge contacts dual rank rohs compliant package option ? 200 pin so-dimm ? pcb C 30.00mm (1.181") max operating frequencies pc2-6400* pc2-5300* pc2-4200 pc2-3200 clock speed 400mhz 333mhz 266mhz 200mhz cl-t rcd -t rp 6-6-6 5-5-5 4-4-4 3-3-3
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs notes: sa2 does not connect to memory connector and is shown only on block diagram sa2 is tied low on memory module for all memory con? gurations pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 51 dq18 101 v cc 151 v ss 2v ss 52 v ss 102 a6 152 v ss 3 dq0 53 dq19 103 a5 153 dqs5# 4 dq4 54 dq28 104 a4 154 dm5 5v ss 55 v ss 105 a3 155 dqs5 6 dq5 56 dq29 106 v cc 156 v ss 7 dq1 57 dq24 107 a2 157 v ss 8v ss 58 v ss 108 a1 158 dq46 9 dqs0# 59 dq25 109 v cc 159 dq42 10 dm0 60 dm3 110 a0 160 dq47 11 dqs0 61 v ss 111 a10/ap 161 dq43 12 v ss 62 v ss 112 ba1 162 v ss 13 v ss 63 dqs3# 113 ba0 163 v ss 14 dq6 64 dq30 114 v cc 164 dq52 15 dq2 65 dqs3 115 ras# 165 dq48 16 dq7 66 dq31 116 we# 166 dq53 17 dq3 67 v ss 117 v cc 167 dq49 18 v ss 68 v ss 118 cs0# 168 v ss 19 v ss 69 dq26 119 cas# 169 v ss 20 dq12 70 cb4 120 odt0 170 dm6 21 dq8 71 dq27 121 cs1# 171 dqs6# 22 dq13 72 cb5 122 a13 172 v ss 23 dq9 73 v ss 123 v cc 173 dqs6 24 v ss 74 v ss 124 v cc 174 dq54 25 v ss 75 cb0 125 odt1 175 v ss 26 dm1 76 dm8 126 ck 176 dq55 27 dqs1# 77 cb1 127 nc/cs3# 177 dq50 28 v ss 78 v ss 128 ck# 178 v ss 29 dqs1 79 v ss 129 dq32 179 dq51 30 dq14 80 cb6 130 v ss 180 dq60 31 v ss 81 dqs8# 131 v ss 181 v ss 32 dq15 82 cb7 132 dq36 182 dq61 33 dq10 83 dqs8 133 dq33 183 dq56 34 v ss 84 v cc 134 dq37 184 v ss 35 dq11 85 v ss 135 dqs4# 185 dq57 36 dq20 86 cb2 136 v ss 186 dm7 37 v ss 87 cke0 137 dqs4 187 v ss 38 dq21 88 cb3 138 dm4 188 dq62 39 dq16 89 cke1 139 v ss 189 dqs7# 40 v ss 90 v ss 140 v ss 190 v ss 41 dq17 91 nc/cs2# 141 dq34 191 dqs7 42 nc 92 ba2 142 dq38 192 dq63 43 v ss 93 v cc 143 dq35 193 dq58 44 dm2 94 nc 144 dq39 194 sda 45 dqs2# 95 a12 145 v ss 195 v ss 46 v ss 96 a11 146 v ss 196 scl 47 dqs2 97 a9 147 dq40 197 dq59 48 dq22 98 v cc 148 dq44 198 sa1 49 v ss 99 a7 149 dq41 199 v cc spd 50 dq23 100 a8 150 dq45 200 sa0 pin names pin name function a0-a13 address inputs a10/ap address input/auto precharge ba0 - ba2 sdram bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobes dqs0#-dqs8# data strobes negative odt0, odt1 on-die termination control ck,ck# clock inputs, positive/negative cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable v cc core power (1.8v) v ss ground sa0-sa1 spd address sda serial data input/output v ref input/output reference dm0-dm8 data-in mask v ccspd serial eeprom power supply scl serial presence detect(spd) clock input nc no connect
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ccspd v cc v ref v ss serial pd ddr2 sdrams ddr2 sdrams ddr2 sdrams pll ck0 ck ck# ck0# 120? ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# cs1# cs0# dqs0 dqs0# dm0 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs4 dqs4# dm4 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs1 dqs1# dm1 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs5 dqs5# dm5 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs2 dqs2# dm2 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs6 dqs6# dm6 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs3 dqs3# dm3 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs7 dqs7# dm7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm# cs# dqs dqs# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs# dqs dqs# dqs8 dqs8# dm8 cs0# cs1# ba0 - ba2 a0 - a13 ras# cas# we# cke0 cke1 odt0 odt1 cs0# : ddr2 sdrams cs1# : ddr2 sdrams ba0 - ba2 : ddr2 sdrams a0 - a13 : ddr2 sdrams ras# : ddr2 sdrams cas# : ddr2 sdrams we# : ddr2 sdrams cke0 : ddr2 sdrams cke1 : ddr2 sdrams odt0 : ddr2 sdrams odt1 : ddr2 sdrams note: all resistor values are 22 ohms unless otherwise speci? ed.
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions all voltages referenced to v ss parameter symbol rating units notes min. type max. supply voltage v cc 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v cc 0.50 x v cc 0.51 x v cc v1 i/o termination voltage v tt v ref -0.04 v ref v ref +0.04 v 2 notes: 1 v ref is expected to equal v cc /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/-1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed +/-2 percent of v ref . this measurement is to be taken at the nearest v ref bypass capacitor. 2. v tt in sot applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . absolute maximum ratings symbol parameter min max units v cc voltage on v cc pin relative to v ss -1.0 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 ?c t case device operating temperature 0 85 ?c i l input leakage current; any input 0v wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs operating temperature condition parameter symbol rating units notes operating temperature toper 0 to 85 c 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jeded jesd51.2 2. at 0c - 85c, operation temperature range, all dram speci? cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih (dc) v ref + 0.125 v cc + 0.300 v input low (logic 0) voltage v il (dc) -0.300 v ref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage ddr2-400 & ddr2-533 v ih (ac) v ref + 0.250 - v input low (logic 1) voltage ddr2-667 v ih (ac) v ref + 0.200 - v input low (logic 0) voltage ddr2-400 & ddr2-533 v il (ac) - v ref - 0.250 v input low (logic 0) voltage ddr2-667 v il (ac) - v ref - 0.200 v input/output capacitance t a = 25c, f = 100mhz parameter symbol min max units input capacitance (a0~a13, ba0~ba2, ras#, cas#, we#) c in1 22 40 pf input capacitance (cke0, cke1), (odt0, odt1) c in2 13 22 pf input capacitance (cs0# ~ cs1#) c in3 13 22 pf input capacitance (ck, ck#) c in4 67pf input capacitance (dm0 ~ dm8), (dqs0 ~ dqs8) c in5 (665) 9 11 pf c in5 (534, 403) 9 12 pf input capacitance (dq0 ~ dq63), (cb0 ~ cb7) c out1 (665) 9 11 pf c out1 (534, 403) 9 12 pf
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 i cc specifications and conditions includes ddr2 sdram components only 0c t case < +70c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v symbol proposed conditions 806 665 534 403 units i cc0* operating one bank active-precharge current; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,218 1,173 1,128 ma i cc1* operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ), t rcd = t rcd (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w tbd 1,308 1,263 1,218 ma i cc2p** precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 516 516 516 ma i cc2q** precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 1,020 930 930 ma i cc2n** precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching tbd 1,110 1,020 1,020 ma i cc3p** active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 840 750 750 ma slow pdn exit mrs(12) = 1 tbd 516 516 516 ma i cc3n** active standby current; all banks open; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 1,200 1,110 1,110 ma i cc4w* operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,803 1,578 1,443 ma i cc4r* operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w tbd 1,803 1,578 1,443 ma i cc5** burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 4,260 4,170 4,080 ma i cc6** self refresh current; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating tbd 108 108 108 ma i cc7* operating bank interleave read current; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data pattern is same as i cc4r ; refer to the following page for detailed timing conditions tbd 3,108 2,928 2,748 ma note: i cc speci? cation is based on samsung components. other dram manufacturers speci? cation may be different. * value calculated as one module rank in this operation condition, and all other module ranks in i cc2p (cke low) mode. ** value calculated re? ects all module ranks in the operating condition.
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters & specifications ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit clock clock cycle time cl = 6 t ck (6) tbd tbd ps cl = 5 t ck (5) tbd tbd 3,000 8,000 ps cl = 4 t ck (4) tbd tbd 3,750 8,000 3,750 8,000 5,000 8,000 ps cl = 3 t ck (3) tbd tbd 5,000 8,000 5,000 8,000 5,000 8,000 ps ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck half clock period t hp tbd tbd min (t ch , t cl ) min (t ch , t cl ) min (t ch , t cl ) ps clock jitter t j i t tbd tbd -125 125 -125 125 -125 125 ps data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz tbd tbd t ac max t ac max t ac max ps data-out low-impedance window from ck/ck# t lz tbd tbd t ac min t ac max t ac min t ac max t ac min t ac max ps dq and dm input setup time relative to dqs t ds tbd tbd 100 100 150 ps dq and dm input hold time relative to dqs t dh tbd tbd 175 225 275 ps dq and dm input pulse width (for each input) t d i pw tbd tbd 0.35 0.35 0.35 t ck data hold skew factor t qhs tbd tbd 340 400 450 ps dqdqs hold, dqs to ? rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs ps data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq ns data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqsdq skew, dqs to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres tbd tbd 000p s dqs write preamble t wpre tbd tbd 0.25 0.25 0.25 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck write command to ? rst dqs latching transition t dqss tbd tbd wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck address and control input setup time t is tbd tbd 200 250 350 ps address and control input hold time t ih tbd tbd 275 375 475 ps address and control input hold time t ccd tbd tbd 222t ck ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different. continued on next page
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters (cont'd) ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit command and address active to active (same bank) command t rc tbd tbd 55 60 65 ns active bank a to active bank b command t rrd tbd tbd 7.5 7.5 7.5 ns active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 37.5 37.5 37.5 ns active to precharge command t ras tbd tbd 40 70,000 40 70,000 40 70,000 ns internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns write recovery time t wr tbd tbd 15 15 15 ns auto precharge write recovery + precharge time t dal tbd tbd t wr + t rp t wr + t rp t wr + t rp ns internal write to read command delay t wtr tbd tbd 7.5 7.5 10 ns precharge command period t rp tbd tbd 15 15 15 ns precharge all command period t rpa tbd tbd t rp+ t ck t rp+ t ck t rp+ t ck ns load mode command cycle time t mrd tbd tbd 222t ck cke low to ck,ck# uncertainty t delay tbd tbd t is+ t ck + t ih t is+ t ck + t ih t is+ t ck + t ih ns self refresh refresh to active of refresh to refresh command interval t rfc tbd tbd 127.5 70,000 127.5 70,000 127.5 70,000 ns average periodic refresh interval t ref i tbd tbd 7.8 7.8 7.8 s exit self refresh to non-read command t xsnr tbd tbd t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference ti sxr tbd tbd t is t is t is ps odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t aon tbd tbd t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 ps odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn-on (power-down mode) t aonpd tbd tbd t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 ps odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 222t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 6 - al 6 - al 6 - al t ck a exit precharge power-down to any non- read command. t xp tbd tbd 222t ck cke minimum high/low time t cke tbd tbd 333t ck ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different.
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 6.35 (0.250) max 1.10 (0.043) 0.90 (0.035) pin 1 67.75 (2.667) 67.45 (2.656) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ pin 199 pin 200 pin 2 front view 2.15 (0.085) 6.00 (0.236) 2.504 (63.60) 2.55 (0.100) 1.00 (0.039) typ typ back view 30.15 (1.187) 29.85 (1.175) 47.40 (1.866) typ 11.40 (0.449) typ 4.2 (0.165) typ 4.10 (0.161) (2x) 3.90 (0.154) package dimensions for ad4 * all dimensions are in millimeters and (inches) tolerances: 0.13 (0.005) unless otherwise speci? ed ordering information for d4 part number clock/data rate speed cas latency t rcd t rp height* wv3hg2128m72eeu806ad4-xg 400mhz/800mb/s 6 6 6 30.00mm (1.181") wv3hg2128m72eeu665ad4-xg 333mhz/667mb/s 5 5 5 30.00mm (1.181") wv3hg2128m72eeu534ad4-xg 266mhz/533mb/s 4 4 4 30.00mm (1.181") wv3hg2128m72eeu403ad4-xg 200mhz/400mb/s 3 3 3 30.00mm (1.181") notes: ? rohs product. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory component source control. the place holder for this is shown as a l ower case "-x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide wv 3 h g 2 128m 72 e e u xxx ad4 x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width x8 1.8v unbuffered speed (mb/s) package 200 pin so-dimm component vendor name (m = micron) (s = samsung) g = rohs compliant
wv3hg2128m72eeu-ad4 february 2006 rev. 0 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 2gb C 2x128mx72 ddr2 sdram unbuffered, ecc w/pll revision history rev # history release date status rev 0 created february 2006 advanced
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